Merced, EPIC, & IA64 Explained

Hardware translation

Merced, Intel's first IA64 processor will provide full IA32 and PA-RISC (HPs PA-RISC series RISC processors instruction set) by means of hardware translation. Intel was debating on whether or not to add an entire separate IA32 core; along with a PA-RISC core, but decided against it because it would be inefficient use of die-size, since many features are already included. Hardware translation takes IA32 code and runs it on an IA64 processor "on-the-fly". The advantage of Hardware translation over a new IA32 core is that the processor can take advantage of 64bit data paths, among other improvements already included in the core. This approach is the most elegant according to Intel, and the route they plan on taking. Merced is expected to perform on par, or faster than the fastest IA32 processor out at the time.

Problems

The first major concern regarding EPIC is that it relies heavily on compilers to perform optimally. While this may not seem like a problem, and really isn't if you look at it from a certain angle; however, not all compilers are created equal. A slow compiler will result in a significant performance loss (as compared to the loss for a RISC or CISC chip). Compiler developers will play an important role in the performance of Merced and other EPIC processors. Good compilers will warrant very good performance, bad compilers will yield very poor performance.

Debugging

Debugging an EPIC application may be somewhat strange due to all the pre-processing and parallelism. Speculation will especially cause some interesting complications during debugging. Good debugging software will need to be written to help developers debug and optimize their code.